? semiconductor components industries, llc, 2000 november, 2000 rev. 1 1 publication order number: mtp10n10el/d mtp10n10el preferred device power mosfet 10 amps, 100 volts, logic level nchannel to220 this power mosfet is designed to withstand high energy in the avalanche and commutation modes. the energy efficient design also offers a draintosource diode with a fast recovery time. designed for low voltage, high speed switching applications in power supplies, converters and pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. ? avalanche energy specified ? sourcetodrain diode recovery time comparable to a discrete fast recovery diode ? diode is characterized for use in bridge circuits ? i dss and v ds(on) specified at elevated temperature maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit draintosource voltage v dss 100 vdc draintogate voltage (r gs = 1.0 m w ) v dgr 100 vdc gatetosource voltage continuous nonrepetitive (t p 10 ms) v gs v gsm 15 20 vdc vpk drain current continuous @ t c = 25 c continuous @ t c = 100 c single pulse (t p 10 m s) i d i d i dm 10 6.0 35 adc apk total power dissipation @ t c = 25 c derate above 25 c total power dissipation @ t c = 25 c (note 1.) p d 40 0.32 1.75 watts w/ c watts operating and storage temperature range t j , t stg 55 to 150 c single pulse draintosource avalanche energy starting t j = 25 c (v dd = 25 vdc, v gs = 5.0 vdc, peak i l = 10 adc, l = 1.0 mh, r g = 25 w ) e as 50 mj thermal resistance junction to case junction to ambient junction to ambient (note 1.) r q jc r q ja r q ja 3.13 100 71.4 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 1. when surface mounted to an fr4 board using the minimum recommended pad size. 10 amperes 100 volts r ds(on) = 22 m w preferred devices are recommended choices for future use and best overall value. device package shipping ordering information mtp10n10el to220ab 50 units/rail to220ab case 221a style 5 1 2 3 4 http://onsemi.com nchannel d s g marking diagram & pin assignment mtp10n10el = device code ll = location code y = year ww = work week mtp10n10el llyww 1 gate 3 source 4 drain 2 drain
mtp10n10el http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics draintosource breakdown voltage (v gs = 0 vdc, i d = 0.25 madc) temperature coefficient (positive) v (br)dss 100 115 vdc mv/ c zero gate voltage drain current (v ds = 100 vdc, v gs = 0 vdc) (v ds = 100 vdc, v gs = 0 vdc, t j = 125 c) i dss 10 100 m adc gatebody leakage current (v gs = 15 vdc, v ds = 0 vdc) i gss 100 nadc on characteristics (note 2.) gate threshold voltage (v ds = v gs , i d = 250 m adc) threshold temperature coefficient (negative) m v gs(th) 1.0 1.45 4.0 2.0 vdc mv/ c static draintosource onresistance (v gs = 5.0 vdc, i d = 5.0 adc) r ds(on) 0.17 0.22 ohm draintosource onvoltage (v gs = 5.0 vdc, i d = 10 adc) (v gs = 5.0 vdc, i d = 5.0 adc, t j = 125 c) v ds(on) 1.85 2.6 2.3 vdc forward transconductance (v ds = 8.0 vdc, i d = 5.0 adc) g fs 5.0 7.9 mhos dynamic characteristics input capacitance (v 25 vd v 0 vd c iss 741 1040 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f=10 mhz) c oss 175 250 reverse transfer capacitance f = 1 . 0 mh z ) c rss 18.9 40 switching characteristics (note 3.) turnon delay time t d(on) 11 20 ns rise time (v dd = 50 vdc, i d = 10 adc, t r 74 150 turnoff delay time (v dd = 50 vdc , i d = 10 adc , v gs = 5.0 vdc, r g = 9.1 w ) t d(off) 17 30 fall time gs g ) t f 38 80 gate charge q t 9.3 15 nc (see figure 8) ( v ds = 80 vdc, i d = 10 adc, q 1 2.56 (v ds = 80 vdc , i d = 10 adc , v gs = 5.0 vdc) q 2 4.4 gs ) q 3 4.6 sourcedrain diode characteristics forward onvoltage (note 2.) (i s = 10 adc, v gs = 0 vdc) (i s = 10 adc, v gs = 0 vdc, t j = 125 c) v sd 0.98 0.898 1.6 vdc reverse recovery time t rr 124.7 ns e e se eco e y e (i 10 adc v 0 vdc t a 86 s (i s = 10 adc, v gs = 0 vdc, di s /dt = 100 a/ m s) t b 38.7 reverse recovery stored charge di s /dt = 100 a/ m s) q rr 0.539 m c internal package inductance internal drain inductance (measured from the drain lead 0.25 from package to center of die) l d 4.5 nh internal source inductance (measured from the source lead 0.25 from package to source bond pad.) l s 7.5 2. pulse test: pulse width 300 m s, duty cycle 2.0%. 3. switching characteristics are independent of operating junction temperature.
mtp10n10el http://onsemi.com 3 typical electrical characteristics r ds(on) , drain-to-source resistance (ohms) figure 1. onregion characteristics figure 2. transfer characteristics figure 3. onresistance versus drain current and temperature i d , drain current (amps) figure 4. onresistance versus drain current and gate voltage figure 5. onresistance variation with temperature v ds , drain-to-source voltage (volts) figure 6. draintosource leakage current versus voltage i dss , leakage (na) t j = 25 c v gs = 5 v 10 v v gs = 0 v 04060 1 100 20 100 t j = 125 c 0.25 0.2 10 510 20 15 100 c d i , drain current (amps) 10 5 0 02 5 3 1 v ds , drain-to-source voltage (volts) v gs = 10 v 7 v 3.5 v 4 v 5 v t j = 25 c d i , drain current (amps) 5 0 12 34 5 v gs , gate-to-source voltage (volts) v ds 5 v -55 c t j = 100 c r ds(on) , drain-to-source resistance (ohms) 0.35 0.25 0.15 0.05 0510 i d , drain current (amps) v gs = 5 v t j = 25 c 100 c -55 c 0.15 0.1 0 r ds(on) , drain-to-source resistance (normalized) t j , junction temperature ( c) v gs = 5 v i d = 5 a -50 0 50 100 150 125 -25 25 75 2 1.5 1 0.5 0 4 15 20 4.5 v 25 c 15 20 15 20 3 v 2 v 10 80
mtp10n10el http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. gate-to-source or drain-to-source voltage (volts) figure 7. capacitance variation c, capacitance (pf) 10 0 10 15 25 v gs v ds t j = 25 c v ds = 0 v v gs = 0 v 1400 1000 0 20 c iss c oss c rss 55 c iss c rss 1800 1200 200 1600 400 600 800
mtp10n10el http://onsemi.com 5 q g , total gate charge (nc) draintosource diode characteristics v sd , source-to-drain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) figure 9. resistive switching time variation versus gate resistance figure 8. gatetosource and draintosource voltage versus total charge 0.5 0.9 1.0 0 10 0.8 0.6 0.7 6 2 4 8 v gs = 0 v t j = 25 c 12 8 4 0 02 4 6 8 90 v ds , drain-to-source voltage (volts ) v gs , gate-to-source voltage (volts) 75 45 30 15 0 t j = 25 c i d = 10 a q t q 2 q 3 v gs t, time (ns) 1000 100 10 1 1 10 100 r g , gate resistance (ohms) t j = 25 c i d = 10 a v ds = 100 v v gs = 5 v t d(off) t d(on) t f t r v ds 10 60 q 1 safe operating area the forward biased safe operating area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistancegeneral data and its use.o switching between the offstate and the onstate may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. although many efets can withstand the stress of draintosource avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated.
mtp10n10el http://onsemi.com 6 safe operating area figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b figure 12. maximum avalanche energy versus starting junction temperature figure 11. maximum rated forward biased safe operating area figure 13. thermal response , single pulse drain-to-source as e t j , starting junction temperature ( c) avalanche energy (mj) i d = 10a 30 20 10 0 25 50 75 100 125 150 100 10 1 0.1 0.1 1 10 100 100 m s 10 m s 1 ms 10 ms dc v ds , drain-to-source voltage (volts) i d , drain current (amps) r ds(on) limit thermal limit package limit v gs = 20 v single pulse t c = 25 c 1 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 t, time (seconds) d = 0.5 0.2 0.1 0.05 0.02 0.01 r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 single pulse 40 50 r(t), normalized effective transient thermal resistance
mtp10n10el http://onsemi.com 7 package dimensions to220 threelead to220ab case 221a09 issue aa style 5: pin 1. gate 2. drain 3. source 4. drain notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.147 3.61 3.73 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.018 0.025 0.46 0.64 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 --- 1.15 --- z --- 0.080 --- 2.04 b q h z l v g n a k f 123 4 d seating plane t c s t u r j
mtp10n10el http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mtp10n10el/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
|
